Call for Comming Issue

Volume 2, Issue 6 June 2014

S.No. Title Page No.
A parameterized secure interface for SL-SOC Verification
Abstract: A system-level SOC verification methodology supported hardware accelerator is projected during this paper. The storage mapping relationship is meant in step with storage characteristics of the hardware accelerator, and also the whole testbench is place into the accelerator directly, leading to a fast migration to accelerator associated an optimized memory space. so as to make sure the comprehensiveness, complexness and credibleness, the system feature description is extracted from totally different application eventualities, and also the take a look at cases ar derived from the ways of information flow and management flow. to boot, the system debugging is simplified by dominant the acceleration process with the tactic of triggerdriver- based state transition diagram. By adopting the system-level verification methodology projected during this paper, RTL style of a DSP chip is verified and also the experiment results demonstrate associate Brobdingnagian acceleration result and a high accuracy in bug locating. Finally the DSP chip is enforced in zero.18um CMOS method and it works properly.
An open concurrent NPVR System for an IPTV Platform
Abstract: IPTV (Internet Protocol Television) is one in every of the most net applications developed in recent years. It provides associate new kind of multimedia system services within the variety of streaming media, delivers real time contents to users directly, and supports new services like user interactive TV programs. during this paper, we have a tendency to style and implement a crossplatform net IPTV systems supported the useful definitions of the OIPF (Open IPTV Forum) normal. we have a tendency to implement many multimedia system streaming functions, as well as video transfer, NPVR (Network Personal Video Recorder), VoD (Video on Demand) and live video services.
A reliable Radial Distribution Networks with their effects
Abstract: In designing of radial power distribution system, optimum feeder routing play a very important role. This paper proposes a straightforward approach to optimize the full annual value of the network, that represents investment value (fixed cost) for itinerary in addition as station and operational prices (energy loss costs). the most objective of this methodology is to search out the optimum route for every load purpose in massive size wattage distribution system and to get the optimum radial network. associate rule is projected for simplified case study of a feeder network. The projected rule is valid mistreatment MATLAB and therefore the result therefore obtained is compared with the prevailing results. The numerical results with completely different take a look at cases square measure mentioned, therefore confirming the effectiveness of this approach.
An optimized functional theorem proved for a UHF RFID Tag
Abstract: Clock accuracy is vital to the performance of ultrahigh frequency (Ultra High Frequency) RFID (Radio Frequency Identification) tag, particularly for the encoder in baseband. to cut back the bit error rate of the responded knowledge from tag, a unique clock strategy is projected during this paper, that generates a high accuracy clock for the encoder by reckoning the preamble of the commands from reader. Moreover, for reducing the chip space and also the power consumption, a unique CRC (Cyclic Redundancy Check) generator is meant, that reuses the resource and fulfills a no-gap-link between the responded knowledge and CRC code. The baseband of tag is enforced in an exceedingly zero.18μm CMOS method and its space is 75479μm2.Simulation results show that the frequency variation of the clock is among an inexpensive vary.





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